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SV51002
2014.01.10
Shared Arithmetic Mode
1-11
before connecting to the next LAB. This leaves the other half of the ALMs in the LAB available for
implementing narrower fan-in functions in normal mode. Carry chains that use the top five ALMs in the
first LAB carry into the top half of the ALMs in the next LAB in the column. Carry chains that use the bottom
five ALMs in the first LAB carry into the bottom half of the ALMs in the next LAB within the column. You
can bypass the top-half of the LAB columns and bottom-half of the MLAB columns.
The Quartus II Compiler creates carry chains longer than 20 ALMs (10 ALMs in arithmetic or shared
arithmetic mode) by linking LABs together automatically. For enhanced fitting, a long carry chain runs
vertically, allowing fast horizontal connections to the TriMatrix memory and DSP blocks. A carry chain can
continue as far as a full column.
Shared Arithmetic Mode
The ALM in shared arithmetic mode can implement a 3-input add in the ALM.
This mode configures the ALM with four 4-input LUTs. Each LUT either computes the sum of three inputs
or the carry of three inputs. The output of the carry computation is fed to the next adder using a dedicated
connection called the shared arithmetic chain.
Figure 1-12: ALM in Shared Arithmetic Mode for Stratix V Devices
shared_arith_in
datae0
4-Input
LUT
carry_in
labclk
datac
datab
dataa
4-Input
LUT
reg0
datad
4-Input
LUT
reg1
To General or
Local Routing
datae1
4-Input
LUT
shared_arith_out
reg2
reg3
carry_out
Shared Arithmetic Chain
The shared arithmetic chain available in enhanced arithmetic mode allows the ALM to implement a 3-input
adder. This significantly reduces the resources necessary to implement large adder trees or correlator
functions.
The shared arithmetic chain can begin in either the first or sixth ALM in a LAB.
Similar to carry chains, the top and bottom half of the shared arithmetic chains in alternate LAB columns
can be bypassed. This capability allows the shared arithmetic chain to cascade through half of the ALMs in
Logic Array Blocks and Adaptive Logic Modules in Stratix V Devices
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